1. Technical Field
This disclosure relates to semiconductor devices and more particularly, to a method for forming deep trench top isolation layers for semiconductor memories by employing a selective sub-atmospheric chemical vapor deposition oxide (SACVD-oxide).
2. Description of the Related Art
Semiconductor memories such as dynamic random access memories (DRAM) typically include memory cells with storage nodes. Generally these storage nodes are formed within deep trenches etched into substrates of the semiconductor memory chip. The storage nodes are accessed using an access transistor which allows charge to be stored in the storage node or retrieves charge from the storage depending on whether the desired action is a read or write function. It is often necessary to ensure that the storage node is sufficiently electrically isolated from a gate conductor through the top of the deep trench.
One way to ensure sufficient electrical isolation of the storage node through the top of the trench is to provide a top trench isolation layer over the storage node. The storage nodes typically include polysilicon material that partially fills the deep trench. During fabrication the polysilicon provides a recess remaining at the top of the trench. An oxide (silicon dioxide) is deposited over the surface of the semiconductor device. During the oxide deposition, oxide is formed over the polysilicon in the trench. Other portions of the deposited oxide are removed by planarizing the surface of the semiconductor device and by optionally recessing the oxide to leave a 30-50 nm oxide layer at the bottom of the recess. This oxide layer is referred to as a trench top oxide or isolation. The oxide layer alone may not provide sufficient isolation however to fulfill reliability requirements.
In the case where vertical transistors are fabricated on the memory device, a buried strap portion of the storage node, i.e., the portion directly below the top trench oxide must outdiffuse to connect to a vertical transistor channel which extends along a gate conductor in the deep trench above the top trench oxide. In this way, when the vertical transistor conducts, a connection is made between the storage node and a bit line. The channel must be electrically isolated from the gate conductor. Therefore, an insulating layer is provided therebetween, typically an oxide layer formed by oxidizing a portion of the polysilicon of the gate conductor within the deep trench and the channel.
The oxide recessing is difficult to control. This difficulty introduces a lot of variability in the remaining oxide layer thickness. The trench top oxide thickness is an important parameter and must be maintained in order for the semiconductor memory to work properly. As described above, the trench top oxide electrically isolates the storage node from the gate conductor of the semiconductor device.
Therefore, a need exists for a trench top dielectric having a controlled thickness which can withstand the processing steps needed to fabricate a memory device.